The present invention is directed to multi-core integrated circuits and, more particularly, to testing a multi-core integrated circuit with parallel scan test data inputs and outputs.
Integrated circuits (ICs) are commonly tested using automatic test equipment (ATE) during manufacture to detect hardware defects. A device under test (DUT) may have design-for-testability (DFT) features that facilitate the automatic testing. The DFT features often include scan test capability in which elements of the IC, such as latches or flip-flops, are connected temporarily in scan chains to test the functionality of the elements. Test data input signals are applied to a test data input (TDI) pads to shift test patterns into the IC through the scan chains during test mode operation. The DUT is returned to functional operation during one or more capture clock cycles, and the resulting signals are shifted out through the scan chains to test data output (TDO) pads and checked against expected valid outputs. One industry standard that is widely used in automatic testing of ICs (and other circuits) is the Joint Test Action Group (JTAG) standard IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture.
Multi-core ICs have more than one core that ensure given circuit functions, such as central processor cores (CPU), digital signal processors (DSP), Serializer/Deserializers (SerDes), phase-locked loops (PLLs), digital-to-analog converters (DAC), analog-to-digital converters (ADC) and physical layer units (PHYs). Scan testing such multi-core ICs commonly involves testing several cores that are each configured in test mode with a plurality of scan chains. A conventional approach provides m TDI and m TDO pads for m chains for each core, and a total of 2*m*n TDI and TDO pads for n cores. However, it is important to reduce the number of connection pads, and therefore the number of external pins or leads on ICs, especially for some types of devices. Another conventional approach uses only m TDI and m TDO pads, common to all the cores, but applies the test data to the cores one after the other, which multiplies the test time by the number n of cores.
Cores of a multi-core IC of the same type commonly have nominally similar functional characteristics, and are tested by similar TDI test patterns shifted through similar scan chains in the cores. Another conventional approach provides m common TDI pads for m similar chains in each of the nominally similar cores and applies the TDI signals simultaneously to the corresponding chains in all the cores in parallel. This approach avoids increasing the test time. However, there are still respective TDO pads for each chain and each core, so that there are a total of m*(n+1) TDI and TDO pads for n cores.
It would be advantageous to scan test nominally similar cores of a multi-core IC simultaneously, in parallel using common scan TDI pads and common scan TDO pads.